To improve the operational speed of integrated circuit devices, integrated circuit memory devices have rapidly developed from fast operation mode dynamic random access memories (DRAMs), such as fast page mode DRAMs or extended data output (EDD) DRAMs, to SDRAMs and from SDRAMs to dual data rate (DDR) DRAMs. A number of DRAM manufacturing companies are currently researching the next generation of memory devices after the DDR SDRAMs. For example, the next generation may use DDR2 SDRAMs having a 4-bit prefetch scheme instead of the conventional DDR SDRAMs having a 2-bit prefetch scheme.
The Joint Electronic Device Engineering Council (JEDEC) recommended that DDR2 SDRAMs use a 4-bit prefetch scheme as well as a fixed burst length of 4-bits. In integrated circuit memory devices having a 4-bit prefetch scheme and a fixed burst length of 4-bits, 2-bits of a 4-bit input column address signal that activates a plurality of column select lines are not utilized. In other words, if 2-bits of the 4-bit column address signal are not utilized, only four column select lines may be automatically activated by the column address signal. Furthermore, in integrated circuit memory devices having a 4-bit prefetch scheme and a fixed burst length of 4-bits, the order of data is determined based on a first input column address and the type of address increase scheme used, for example, a sequential address increase scheme or an interleave address increase scheme.
The four column select lines that correspond to the four possible modes using 2-bits of the 4-bit column address signal, i.e., 00, 01, 10, and 11, respectively, are activated in a mode where a burst length is 4-bits, regardless of the starting column address. For example, if the 2-bits of the start column address are 00, the 2-bits of a column address corresponding to a column select line which have to be generated with the start column address 00 are 01, 10, or 11. Accordingly, if the start column address is 01, the 2-bits of a column address corresponding to a column select line which have to be generated with the start column address 01 are 10, 11, or 00.
As described above, if a burst length of 4-bits is used with a 4-bit prefetch scheme, the number of bits to be prefetched is four and the number of sequentially input/output data, i.e., the burst length, is 4-bits. Accordingly, since these lengths are the same, a mode where the burst length is 4-bits may be realized in an integrated circuit memory device using the 4-bit prefetch scheme. However, if the burst length is 8-bits not all the column select lines may be selected using 2-bits of the column address as discussed above. To provide the possibility of eight column select lines, 3-bits are considered if a sequential address increase scheme is used. However, 3-bits do not have to be considered if an interleave address increase scheme is used.
Conventional integrated circuit memory devices having a 2-bit prefetch scheme and a burst length of 4-bits typically include an address counter. The address counter generates addresses corresponding to column select lines that will be generated for the next cycle using 2-bits of the 4-bit column address signal. Therefore, it may be difficult for the integrated circuit memory device using a 4-bit prefetch scheme and a burst length of 8-bits to support a sequential address increase scheme, because as discussed above, 3-bits are typically considered. Accordingly, JEDEC recommends that the burst length of 4-bits be fixed in a DDR2 SDRAM.
An integrated circuit memory device using the 4-bit prefetch scheme is likely to have an address counter which generates addresses corresponding to column select lines that will be generated for next cycle. However, this 4-bit prefetch scheme may be complicated. Furthermore, if the clock cycles are reduced, the internal margin of the integrated circuit device may become short, limiting the operational frequency of the integrated circuit device.
The demand for a burst length of 8-bits has increased because the speed of the integrated circuit memory device can be increased accordingly. If the number of bits to be prefetched is increased to increase the speed of the integrated circuit memory device, the number of internal data input/output (I/O) lines is also typically increased. Some conventional SDRAMs may operate in a mode where the burst length is 8-bits and a nibble sequential address increase scheme is used to meet the demand for the burst length of 8-bits. However, it may be complicated to realize general SDRAMs for supporting the burst length of 8-bits. This may also present difficulties in supporting the sequential address increase scheme, which is generally used in SDRAMs using a prefetch scheme.
SDRAMs using the prefetch scheme typically use the sequential address increase scheme or the interleave address increase scheme. However, SDRAMs using the nibble sequential address increase scheme typically do not support a normal sequential address increase scheme.
Accordingly, integrated circuit devices that support a burst length of 8-bits or twice the number of bits to be prefetched, for example, 4-bits, that can support both sequential and interleave address increase schemes may be desirable.